普通触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Dchu IS
PORT (CLK,D:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END;
ARCHITECTURE FFQ OF Dchu IS
SIGNAL Q1:STD_LOGIC;
BEGIN PROCESS (CLK,Q1)
BEGIN
IF CLK’EVENT AND CLK=’1′
THEN Q1<=D; END IF;
END PROCESS;
Q<=Q1; END FFQ;
,
普通触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Dchu IS
PORT (CLK,D:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END;
ARCHITECTURE FFQ OF Dchu IS
SIGNAL Q1:STD_LOGIC;
BEGIN PROCESS (CLK,Q1)
BEGIN
IF CLK’EVENT AND CLK=’1′
THEN Q1<=D; END IF;
END PROCESS;
Q<=Q1; END FFQ;
